The present invention relates to semiconductor devices and methods of forming the same, and more particularly, to nonvolatile semiconductor devices and methods of forming the same.
Semiconductor memory devices may be classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. A volatile semiconductor memory device typically loses stored data when its power supply is interrupted, while a non-volatile semiconductor memory device typically retains stored data even when its power supply is interrupted.
A flash memory is typically a highly integrated non-volatile device having advantages of an erasable programmable read-only memory (EPROM) and advantages of an electrically erasable programmable read-only memory (EEPROM). Types of flash memory devices include NOR-type flash memory devices and NAND-type flash memory devices. A NAND-type flash memory device may be advantageous with respect to high integration as it typically includes a basic unit including a string of memory cells that have common controls.
FIGS. 1 and 2 are a circuit diagram and a cross-sectional view, respectively, of a conventional non-volatile memory device. Referring to FIGS. 1 and 2, a NAND flash memory cell array includes a string select line SSL and a ground select line GSL. Word lines WL0-WLn−1 are arranged between the string select line SSL and the ground select line GSL. The string select line SSL, the ground select line GSL, and the word lines WL0-WLn−1 may include a tunnel insulating layer 20, a floating gate 30, an intergate dielectric 40, and a control gate 50. The condition of a program voltage of a selected memory cell MC1i in the NAND flash memory device is shown. A ground voltage GND is applied to a selected bit line BLi and a power supply voltage Vcc is applied to an unselected bit line BLi+1. The power supply voltage Vcc is applied to the string select line SSL, and the ground voltage GND is applied to the ground select line GSL. A ground voltage GND is applied to a common source line CSL. A program voltage Vpgm is applied to a selected word line WL0, and a pass voltage Vpass is applied to unselected word lines WL1-WLn−1. The ground voltage may be applied to a substrate.
While these operations are occurring, it is desirable that a memory cell MC1i+1 of the selected word line WL0 and the unselected bit line BLi+1 be prevented from being programmed. Thus, a channel voltage of the memory cell MC1i+1 of the selected word line WL0 and the unselected bit line BLi+1 may be boosted to a high level to prevent programming of cells connected thereto.
Due to an electric potential difference between a channel region of the ground select line GSL and a channel region boosted to the high level, a strong electric field may be formed in a source/drain region 15 between the ground select line GSL and the word line WL0, which may generate an electron-hole pair. A hole of the electron-hole pair may migrate to the substrate due to a substrate bias (arrow 3), and an electron of the pair may become a hot electron due to a strong horizontal electric field generated by a channel voltage of the ground select line GSL and a channel voltage of the selected word line WL0 (arrow 1). The hot electron may be dispersed toward the selected word line WL0 to be injected into the floating gate 30 (arrow 2). This phenomenon may occur between the string select line SSL and the adjacent word line WLn−1. As a result, program disturbance may occur, i.e., a program inhibit cell may be programmed.
Potential effects of program disturbance will now be described with reference to graphs of FIGS. 3A and 3B, in which a vertical axis represents a threshold voltage Vth and a horizontal axis represents a pass voltage Vpass. FIG. 3A is a graph illustrating word lines WL0, WLn−1 where the program disturbance occurs, and FIG. 3B is a graph illustrating word lines WL1-WLn−1 where the program disturbance does not occur. FIG. 3A shows that, as number of program (NOP) increases, a threshold voltage may rise due to the program disturbance. The rise of the threshold voltage may become significant when a pass voltage Vpass is high. On the other hand, FIG. 3B shows that, even if a number of program (NOP) increases, threshold voltage may not substantially fluctuate.